This disclosure relates generally to the field of integrated circuit (IC) manufacturing, and more specifically to an isolation gate for electrical isolation between semiconductor devices on an IC.
ICs are formed by connecting isolated active devices, which may include semiconductor devices such as field effect transistors (FETs), through specific electrical connection paths to form logic or memory circuits. Therefore, electrical isolation between active devices is important in IC fabrication. A shallow trench isolation (STI) region may be formed in the IC substrate between two active devices to electrically isolate the active devices. An STI region may be formed by forming a trench in the substrate between the active devices by etching, and then filling the trench with an insulating material, such as an oxide. After the STI trench is filled with the insulating material, the surface profile of the STI region may be planarized by, for example, chemical mechanical polishing (CMP).
Edge FETs may have increased non-uniformity due to effects such as different size source/drain (S/D) regions. Placement variation of the gate to silicon edge affects the S/D region size. This variation in S/D region can affect doping profiles, strain levels, and epitaxial growth rates. Dummy gates may be formed at the transition region between an STI and the active silicon to assist with maintaining device uniformity. The dummy gates are formed at each silicon edge; i.e., one dummy gate is located on either edge of the STI region, as is shown in IC 100 of FIG. 1. FIG. 1 illustrates a cross section of an IC 100 having dual dummy gates 103a-b and STI region 104 between active gates 102a-b. Active gates 102a-b are on active regions 101a-b. Active regions 101a-b each include a source, a channel, and a drain region for each of the active gates 102a-b, respectively, to form two active FETs. The devices including active regions 101a-b, with respective active gates 102a-b, are electrically isolated by STI region 104. STI region 104 is filled with an insulating material such as an oxide. An IC such as IC 100 with dual dummy gates 103a-b has a spacing between active regions 101a-b that is about two device pitches. Such spacing between active devices results in an IC having a relatively low device density.